1. Field of the Invention
The present invention relates to integrated circuits. More specifically, the present invention relates to the verification and testing of integrated circuits, such as mask programmable and user programmable gate array integrated circuits.
2. The Prior Art
Numerous types of integrated circuits include a plurality of functional circuit blocks which may be connected together in a custom fashion for particular applications by providing custom interconnect wiring. This custom interconnect wiring is usually implemented in one or more interconnect layers of the integrated circuit as is well known in the art by providing a custom mask for one or more layers of the integrated circuit.
One familiar class of such circuits is known as mask programmable gate array integrated circuits. A particular circuit design is typically first prototyped using a field programmable (i.e., user programmable) gate array integrated circuit. After the circuit design has been verified and tested using the field programmable array as a vehicle, a "hardwired" mask-programmed version of the circuit is used for volume production to achieve cost reduction benefits.
Before an integrated circuit is placed into volume production, the circuit design must be verified and tested to assure complete functionality, quality, and absence of manufacturing defects. One of the difficulties in verifying designs and testing design functionality on integrated circuits is the difficulty with generating test vectors to test the integrated circuit with high fault coverage. A part of this problem is the inability to fully probe the internal circuit nodes of the chip which are not accessible via the input and output pins of the chip. It would be useful to be able to fully probe the internal nodes of an integrated circuit chip for the purposes of both design verification and functionality testing.
The concern over the ability to completely verify and test a design which has been implemented in a mask-programmed gate array integrated circuit, as well as other similar circuits, has led to numerous verification and testing solutions which are known and used in the art. According to one prior art verification and testing method, the designer develops a series of conventional functional test vectors which are applied to the inputs of the integrated circuit. The behavior of the outputs of the circuit under these test vector input conditions is then observed.
There are several problems with this approach. First, developing a comprehensive set of test vectors requires a significant amount of expertise and is extremely time consuming. In addition, the use of test vectors cannot provide 100% fault coverage, no matter how well they are crafted. Functional test vectors typically provide only about 70% fault coverage for integrated circuits of any appreciable size and complexity. Full functionality of the integrated circuit cannot be guaranteed with such incomplete fault coverage.
Another prior art technique which has been developed is known as automatic test pattern generation ATPG. Algorithms, usually implemented in software programs, are used for generating a specialized set of test vectors. All ATPG schemes require the addition to the integrated circuit of circuitry not used during the normal functioning of the circuit. Use of ATPG techniques can raise fault coverage to over 90%.
One form of ATPG verification and testing scheme utilizes scanning techniques. A scanning verification and test regime utilizes special hardware included on the integrated circuit chip in addition to the functional circuit on the chip. A multistage serial shift register (scan register) or series of daisy chained flip-flop circuits are included on the chip, and have inputs connected to various selected internal circuit nodes on the chip. By clocking a selected serial bit stream into the chip through its input pins and the scan register, the logic states of selected internal circuit nodes may be controlled. In addition, the logic states of selected internal circuit nodes may be observed by extracting the logic states from various internal circuit nodes.
Another verification and test scheme provides an addressable matrix on the integrated circuit, through which the state of selected internal nodes of the circuit may be observed. One such scheme is disclosed in U.S. Pat. No. 4,857,774 to El Ayat et al. Another such scheme is disclosed in U.S. Pat. No. 4,749,947 to Gheewala. While these known addressable matrix techniques may provide up to 100% observability for a given hardwired integrated circuit design, they do not provide for any degree of controllability of internal circuit nodes in integrated circuits.
Currently used ATPG schemes require the circuit designer to analyze the circuit in detail to determine where additional test circuitry is needed. This analysis must be performed prior to implementation of the design in silicon.
An ideal verification and testing scheme for integrated circuits would provide both 100% observability and 100% controllability of internal integrated circuit nodes. Such a scheme would allow for automatic test pattern generation which would provide for 100% fault coverage.
It is an object of the present invention to provide a technique and a circuit, which may be integrated along with the functional circuitry of both hardwired and user programmable integrated circuits, for allowing 100% controllability and 100% observability of internal nodes comprising the inputs and outputs of functional circuit blocks in such an integrated circuit, which allows for automatic test pattern generation for 100% fault coverage of the integrated circuit.
Another object of the present invention is to eliminate testing issues from the critical path of the design cycle of integrated circuits by incorporating additional test circuitry into each functional circuit block of the integrated circuit.